The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a process for fabricating a field effect transistor with a fully depleted channel region and with raised source and drain in SOI (semiconductor on insulator) technology for the field effect transistor having scaled down dimensions of tens of nanometers.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC. dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension 104 and a source extension 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension 104 and the source extension 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate structure 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate structure 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where the MOSFET 100 is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the gate structure 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (Si3N4), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the gate structure 118 and the gate dielectric 116.
As the dimensions of the MOSFET 100 are scaled down to tens of nanometers, short-channel effects degrade the performance of the MOSFET 100. Short-channel effects that result due to the short length of the channel between the drain extension 104 and the source extension 106 of the MOSFET 100 are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the MOSFET 100 become difficult to control with bias on the gate structure 118 with short-channel effects which may severely degrade the performance of the MOSFET.
Referring to FIG. 2, to enhance the control of the electrical characteristics, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 150 is fabricate in SOI (semiconductor on insulator) technology. In SOI technology, a layer of buried insulating material 132 is deposited on the semiconductor substrate 102. The layer of buried insulating material 132 is typically comprised of silicon dioxide (SiO2) when the semiconductor substrate 102 is comprised of silicon. In addition, a thin silicon film 134 is deposited on the layer of buried insulating material 132.
A gate dielectric 136 and a gate structure 138 are formed on the thin silicon film 134. A drain and source dopant is implanted into exposed regions of the thin silicon film 134 to form a drain 142 and a source 144 of the MOSFET 150. A channel region of the MOSFET 150 is the portion of the thin silicon film 134 disposed between the drain 142 and the source 144 and disposed below the gate dielectric 136. The silicon film 134 is relatively thin having a thickness in a range of from about 5 nanometers to about 20 nanometers for example. Thus, the channel region of the MOSFET 150 is fully depleted during operation of the MOSFET 150 with improved control of electrical characteristics of the MOSFET 150, as known to one of ordinary skill in the art of integrated circuit fabrication. Thus, the fully depleted channel region of the MOSFET 150 formed in SOI technology minimizes undesired short-channel effects.
Unfortunately, thick drain and source silicides cannot be formed in the drain 142 and the source 144 of the relatively thin silicon film 134. However, thick silicides for providing contact to the drain 142 and the source 144 are desired for minimizing series resistance at the drain and source of the MOSFET 150. Nevertheless, fabrication of a MOSFET having a fully depleted channel region within a thin silicon film in SOI (semiconductor on insulator) technology is also desired for minimizing undesired short channel effects. Thus, a mechanism is desired for forming thick drain and source silicides for the MOSFET having a fully depleted channel region within a thin silicon film in SOI (semiconductor on insulator) technology.
Accordingly, in a general aspect of the present invention, raised drain and source structures are formed by epitaxial growth of a semiconductor material from sidewalls of a thin film semiconductor island forming the fully depleted channel region, and thick drain and source silicides are formed within the raised drain and source structures.
In one embodiment of the present invention, for fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a film of semiconductor material is deposited on a layer of buried insulating material formed on the semiconductor substrate. A layer of active insulating material is deposited on the film of semiconductor material. A masking material is patterned to form a masking structure, and any portion of the layer of active insulating material and the film of semiconductor material not under the masking structure is etched away. The layer of active insulating material remaining under the masking structure forms an insulating block, and the film of semiconductor material remaining under the insulating block forms a semiconductor island. The masking structure is removed from the top of the insulating block.
A semiconductor material is grown from sidewalls of the semiconductor island to extend up along sidewalls of the insulating block to form a raised drain structure on a first side of the insulating block and the semiconductor island and to form a raised source structure on a second side of the insulating block and the semiconductor island. A drain and source dopant is implanted into the raised drain and source structures. A thermal anneal is performed to activate the drain and source dopant within the raised drain and source structures and such that the drain and source dopant extends partially into the semiconductor island.
The insulating block is etched away to form a block opening, and a gate dielectric is deposited at a bottom wall of the block opening. The block opening is filled with a conductive material to form a gate structure disposed over the semiconductor island. The portion of the semiconductor island disposed under the gate structure forms a channel region that is fully depleted during operation of the field effect transistor. A drain silicide is formed within the raised drain structure, and a source silicide is formed within the raised source structure.
In this manner, the drain and source silicides formed in the raised drain and source structures may be formed to have a higher thickness than the relatively thin semiconductor island to minimize series resistance at the drain and source of the field effect transistor. In addition, the channel region of the field effect transistor formed from the relatively thin semiconductor island is fully depleted during operation to the field effect transistor to minimize undesired short channel effects.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.